The present invention relates to a semiconductor memory device, and more particularly, to a test mode control circuit of a semiconductor memory device and a method for controlling a test mode of the semiconductor memory device.
A test mode is typically used to analyze a failure of a semiconductor memory device such as a dynamic random access memory (DRAM) during the development and mass-production of the semiconductor memory device. The test mode is not a normal function but a special function additionally provided in the DRAM.
The test mode is enabled (or set) when a predetermined test mode command and a test code are inputted. The test mode is disabled (or reset) when a predetermined mode register set (MRS) code is inputted or a system enters a power-up mode.
FIG. 1 illustrates a conventional test mode control circuit of a semiconductor memory device. A signal TRSTPB is a pulse signal having a logic low level when an MRS code is inputted. A signal TSET is a pulse signal having a logic high level, which is generated by the combination of a test mode command and a corresponding test code. Signals TRG1 and TRG2 are generated by decoding the test code. When the test mode command and the test code are inputted, the signals TSET, TRG1 and TRG2 go to logic high level and a node N1 goes to logic low level. As a result, a signal TM goes to logic high level, and the test mode is enabled. The signal TM is a control signal for enabling/disabling the test mode. A signal having the same level is maintained at the node N1 by a latch until the MRS code is inputted.
To analyze failures of a semiconductor memory device, a single test mode may be used or a plurality of test modes may be used. For example, a multibit test, a redundancy cell replacement test, a wafer burn-in test may be performed. Meanwhile, there is a situation where only one test mode should be enabled among the plurality of test modes. To this end, the MRS code should be inputted or a system should enter a power-up mode. Thereafter, a test is re-performed by inputting the test mode command and test codes for target test modes except for undesired test modes. However, such a method causes a test program to be complicated and a test time to be increased as well.
In particular, to reset all the test modes during a package test, the MRS code cannot be inputted but a system should be rebooted because the system does not support it. This makes things complicated and requires much more time. Moreover, the package test is performed using a development board that has an unstable system so that a normal booting cannot be performed even if the system is rebooted.